The use of transistor gate electrodes made of doped polysilicon has long been used in the manufacture of metal oxide silicon (MOS) transistors. The use of doped polysilicon gates becomes problematic, however, as the dimensions of gates and gate dielectrics are reduced. Polysilicon gates can accommodate only a finite amount of dopants. This limitation can result in a depletion of gate charge carriers at the interface between the gate and gate dielectric, when the gate electrode of a device is biased to invert the channel. Consequently, the electrical thickness of the gate dielectric is substantially increased, thereby deteriorating the performance characteristics of the transistor, such as reducing the drive current and switching speed. For instance, the electrical thickness of a gate dielectric in some pMOS transistors can increase from about 1.0 nanometer during accumulation mode, to about 1.8 nanometers during inversion mode. Depletion of the polysilicon gate is a fundamental issue limiting further scaling of MOS devices.
Metal gate stacks are an attractive alternative to polysilicon gates because they have a larger supply of charge carriers than doped polysilicon gates. Metal gates stacks have a lower metal layer and an upper polysilicon layer. When a metal gate stack is inverted, there is no substantial depletion of carriers at the interface between the metal gate layer and the gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate stack is not increased. The integration of manufacturing processes for fabricating metal gate stacks into existing of semiconductor transistors manufacturing processes has been troublesome, however.
Consider, for instance, a conventional gate manufacturing process. Such a process typically involves patterning a polysilicon layer to form a polysilicon gate using photolithography techniques. A photoresist layer and underlying inorganic antireflective coating (IARC) are deposited on the polysilicon layer. The photoresist layer is patterned to define the gate's perimeter, and then removed, leaving the IARC on the polysilicon layer. The IARC is then used as an etch mask for patterning the polysilicon layer to form the polysilicon gate. The IARC is then stripped away using a wet etching process, such as a hot phosphoric acid solution containing a metal removal agent.
If the same process is used to fabricate a metal gate stack, significant problems are encountered. Of course, the IARC can be still be used as the etch mask to pattern the polysilicon and metal layer to form the metal gate stack. However, the wet etch process used to remove the IARC is highly corrosive to the metal in the metal gate stack, thereby causing substantial undercutting of the metal portion of the gate. An undercut metal gate layer, in turn, results in several problems, including a modified gate length, poor definition of source/drain and shallow junction structures, and an increased tendency for the metal gate stack to peel off during subsequent processing steps.
Accordingly, what is needed in the art is a process for fabricating a metal gate stack that is not subject to the same problems as conventional gate fabrication processes and yet is readily incorporated into a method for manufacturing semiconductor devices.